ECE LAB - III (PG Research Lab )(VLSI Design)

research-pec-lab

Objectives of the laboratory:

  • To give exposure of VLSI Design Flow
  • To give exposure for front end VLSI design
  • To give exposure for back end VLSI design
  • VLSI circuit design & Simulation
  • To give exposure of EDA Tool
  • Device Modelling

 

Major Equipments:

  • CADENCE Analog Design Suite
  • CADENCE Digital Design Suite
  • TCAD Software
  • PC i7 core based

 

Types of projects (R&D/Consultancy):

  • Device modelling
  • VHDL/Verilog Based system Design
  • VLSI Circuit Design
  • Low Power design
  • Area Optimization

 

Name of Officials

  • Dr. Neelam Rup Prakash (O/I) 
  • Ms. Jasbir Kaur (Joint O/I)
  • Mr. Tejinder Pal Singh( Astt. Programmer) 
  • Mr. K. K. Dubey (Lab attendant)